The recent development of silicon (Si) substrates with strained layers has increased the options available for design and fabrication of field-effect transistors (FETs). Enhanced performance of n-type metal-oxide-semiconductor (NMOS) transistors has been demonstrated with heterojunction metal-oxide-semiconductor field effect transistors (MOSFETs) built on substrates having strained silicon and relaxed silicon-germanium (SiGe) layers. Tensilely strained silicon significantly enhances electron mobilities. NMOS devices with strained silicon surface channels, therefore, exhibit improved performance with higher switching speeds. Hole mobilities are enhanced in tensilely strained silicon as well, but to a lesser extent for strain levels less than approximately 1.5%. Accordingly, equivalent enhancement of p-type metal-oxide-semiconductor (PMOS) device performance in such surface-channel devices presents a challenge.
Hole mobility enhancement has been demonstrated in highly strained SiGe layers. The formation of such highly strained layers is made difficult by the tendency of these layers to undulate, especially with increasing strain levels, i.e., with high Ge content. This undulation lowers hole mobilities, thereby offsetting the beneficial mobility enhancement provided by the strained layers.
The observed undulation arises from lattice mismatch with respect to an underlying layer, and increases in severity with formation temperature. Unfortunately, the formation of a tensilely strained layer made of, for example, Si, over the compressively strained layer is desirably carried out at a relatively high temperature, e.g., 550° C., to achieve a commercially viable formation rate and uniformity.